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NCV4275 5.0 V Low-Drop Voltage Regulator
This industry standard linear regulator has the capability to drive loads up to 450 mA at 5.0 V. It is available in DPAK and D2PAK. This device is pin-for-pin compatible with Infineon part number TLE4275.
Features http://onsemi.com MARKING DIAGRAMS
DPAK 5-PIN DT SUFFIX CASE 175AA 4275 ALYWW x
* * * * * *
*
5.0 V, 2%, 450 mA Output Voltage Very Low Current Consumption Active RESET Reset Low Down to VQ = 1.0 V 500 mV (max) Dropout Voltage Fault Protection +45 V Peak Transient Voltage -42 V Reverse Voltage Short Circuit Thermal Overload NCV Prefix for Automotive and Other Applications Requiring Site and Control Changes
1 5
1
1 5
D2PAK 5-PIN DS SUFFIX CASE 936A
NCV4275 AWLYYWW
Pin 1. I 1 2. RO Tab, 3. GND* 4. D 5. Q * Tab is connected to Pin 3 on all packages I Error Amplifier + - Current Limit and Saturation Sense Q A WL, L YY, Y WW = Assembly Location = Wafer Lot = Year = Work Week
Bandgap Reference Thermal Shutdown D
ORDERING INFORMATION
Reset Generator Device NCV4275DT NCV4275DTRK GND NCV4275DS NCV4275DSR4 RO Package DPAK DPAK D2PAK D2PAK Shipping 75 Units/Rail 2500 Tape & Reel 50 Units/Rail 800 Tape & Reel
Figure 1. Block Diagram
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
(c) Semiconductor Components Industries, LLC, 2004
1
August, 2004 - Rev. 8
Publication Order Number: NCV4275/D
NCV4275
PIN FUNCTION DESCRIPTION
Pin No. 1 2 3 4 5 Symbol I Description Input; Battery Supply Input Voltage. Bypass to ground with a ceramic capacitor. Reset Output; Open Collector Active Reset (accurate when I > 1.0 V). Ground; Pin 3 internally connected to tab.
NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN N NNNNNNNNNNNNNNNNNNNNNNNN NNNNNNNNNNNNNNNNNNNNNNNN N N NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN NNNNNNNNNN NNNNNNNNNNNNNNNNNNNNNNNN N NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN N NNNNNNNNNN NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN NNNNNNNNNN NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN N NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN N
RO GND D Reset Delay; timing capacitor to GND for Reset Delay function. Q Output; 2.0%, 450 mA output. Use 22 mF, ESR < 5.0 to ground.
MAXIMUM RATINGS
Input [I (DC)]
Rating
Min
Max 45 45 16 25 5.0 7.0 2.0 42 - 150 150
Unit V V V V mA V mA V kV C C C C
-42 - -1.0 -0.3 -5.0 -0.3 -2.0 5.5 2.0 -40 -55 Reflow (SMD styles only) Note 1 Wave Solder (through hole styles only) Note 2 - -
Input [I (Peak Transient Voltage)] Output (Q) Reset Output (RO) Reset Output (RO) Reset Delay (D) Reset Delay (D) Operating Range (I) ESD Susceptibility (Human Body Model) Junction Temperature Storage Temperature Lead Temperature Soldering
240 Peak (Note 3) 260 Peak
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.
THERMAL CHARACTERISTICS
Parameter DPAK 5-PIN PACKAGE Min Pad Board (Note 4) Junction-to-T (psi-JLx, yJLx) ab Junction-to-Ambient (RqJA, qJA) D2PAK 5-PIN PACKAGE 0.4 sq. in. Spreader Board (Note 6) Junction-to-T (psi-JLx, yJLx) ab Junction-to-Ambient (RqJA, qJA) 3.8 74.8 1.2 sq. in. Spreader Board (Note 7) 4.0 41.6 C/W C/W 4.2 100.9 1 Pad Board (Note 5) 4.7 46.8 C/W C/W Test Conditions (Typical Value) Unit
1. 60 seconds max above 183C. 2. 10 seconds max. 3. -5C/+0C allowable conditions. 4. 1 oz. copper, 0.26 inch2 (168 mm2) copper area, 0.62 thick FR4. 5. 1 oz. copper, 1.14 inch2 (736 mm2) copper area, 0.62 thick FR4. 6. 1 oz. copper, 0.373 inch2 (241 mm2) copper area, 0.62 thick FR4. 7. 1 oz. copper, 1.222 inch2 (788 mm2) copper area, 0.62 thick FR4. During the voltage range which exceeds the maximum tested voltage of I, operation is assured, but not specified. Wider limits may apply. Thermal dissipation must be observed closely.
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ELECTRICAL CHARACTERISTICS (I = 13.5 V; -40C < TJ < 150C; unless otherwise noted)
Characteristic Output Output Voltage Output Voltage Output Current Limitation Quiescent Current, Iq = II - IQ Quiescent Current, Iq = II - IQ Quiescent Current, Iq = II - IQ Dropout Voltage Load Regulation Line Regulation Power Supply Ripple Rejection Temperature Output Voltage Drift Reset Timing D and Output RO Reset Switching Threshold Reset Output Low Voltage Reset Output Leakage Current Reset Charging Current Upper Timing Threshold Lower Timing Threshold Reset Delay Time Reset Reaction Time CD = 47 nF CD = 47 nF - Rext > 5.0 k, VQ > 1.0 V VROH = 5.0 V VD = 1.0 V - - 4.5 - - 3.0 1.5 0.2 10 - 4.65 0.2 0 5.5 1.8 0.4 16 1.5 4.8 0.4 10 9.0 2.2 0.7 22 4.0 V V mA mA V V ms ms IQ = 1.0 mA IQ = 250 mA IQ = 400 mA IQ = 300 mA, Vdr = VI - VQ IQ = 5.0 mA to 400 mA V = 8.0 V to 32 V, IQ = 5.0 mA fr = 100 Hz, Vr = 0.5 Vpp - 5.0 mA < IQ < 400 mA, 6.0 V < VI < 28 V 5.0 mA < IQ < 200 mA, 6.0 V < VI < 40 V - 4.9 4.9 450 - - - - -30 -25 - - 5.0 5.0 700 150 10 23 250 15 5.0 60 0.5 5.1 5.1 - 200 15 35 500 30 25 - - V V mA mA mA mA mV mV mV dB mV/k Test Conditions Min Typ Max Unit
TYPICAL PERFORMANCE CHARACTERISTICS
1000 Unstable ESR Region for CVout = 1 mF - 22 mF Maximum ESR for CVout = 1 mF - 22 mF
100
ESR (W)
10 Stable ESR Region Minimum ESR for CVout = 1 mF 0.1 Unstable Region for CVout = 1 mF 0 100 200 300 400 500
1
0.01
OUTPUT CURRENT (mA)
Figure 2. Output Stability with Output Capacitor ESR
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APPLICATION INFORMATION
VI
II CI1 1000 F CI2 100 nF ID CD 47 nF
I
1 NCV4275
5
Q CQ 22 F
IQ Rext 5.0 k
VQ
D
4
3 GND
2
RO
IRO
VRO
Figure 3. Test Circuit
Circuit Description The error amplifier compares a temperature-stable reference voltage to a voltage that is proportional to the output voltage (Q) (generated from a resistor divider) and drives the base of a series transistor via a buffer. Saturation control as a function of the load current prevents oversaturation of the output power device, thus preventing excessive substrate current (quiescent current). Typical drop out voltage at 300 mA load is 250 mV, 500 mV maximum. Test voltage for drop out is 5.0 V input. Stability Considerations The input capacitors (CI1 and CI2) are necessary to control line influences. Using a resistor of approximately 1.0 in series with CI2 can solve potential oscillations due to stray inductance and capacitance. The output or compensation capacitor helps determine three main characteristics of a linear regulator: start-up delay, load transient response and loop stability. The capacitor value and type should be based on cost, availability, size and temperature constraints. A tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero ESR can cause instability. The aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures (-25C to -40C), both the value and ESR of the capacitor will vary considerably. The capacitor manufacturers data sheet usually provides this information. The value for the output capacitor CQ shown in Figure 3 should work for most applications, however it is not necessarily the optimized solution. Stability is guaranteed for CQ > 22 mF and an ESR 5.0 .
Calculating Power Dissipation in a Single Output Linear Regulator The maximum power dissipation for a single output regulator (Figure 4) is:
PD(max) + [VI(max) * VQ(min)] IQ(max) ) VI(max)Iq
(1)
where VI(max) VQ(min) IQ(max)
is the maximum input voltage, is the minimum output voltage, is the maximum output current for the application, Iq is the quiescent current the regulator consumes at IQ(max). Once the value of PD(max) is known, the maximum permissible value of RqJA can be calculated:
T RqJA + 150C * A PD
(2)
The value of RqJA can then be compared with those in the package section of the data sheet. Those packages with RqJA's less than the calculated value in Equation 2 will keep the die temperature below 150C. In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heatsink will be required.
II VI SMART REGULATOR(R) IQ VQ
} Control Features
Iq
Figure 4. Single Output Regulator with Key Performance Parameters Labeled
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Heat Sinks A heat sink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air. Each material in the heat flow path between the IC and the outside environment will have a thermal resistance. Like series electrical resistances, these resistances are summed to determine the value of RqJA:
RqJA + RqJC ) RqCS ) RqSA
(3)
where RqJC is the junction-to-case thermal resistance, RqCS is the case-to-heatsink thermal resistance, RqSA is the heatsink-to-ambient thermal resistance. RqJC appears in the package section of the data sheet. Like RqJA, it too is a function of package type. RqCS and RqSA are functions of the package type, heatsink and the interface between them. These values appear in heat sink data sheets of heat sink manufacturers. Thermal, mounting, and heatsinking considerations are discussed in the ON Semiconductor application note AN1040/D.
VI
t
VQ
< Reset Reaction Time VQ,rt t Reset Charge Current dVD + dt CD
VD
Upper Timing Threshold
Lower Timing Threshold t Reset Delay Time VRO Reset Reaction Time
t Power-on-Reset Thermal Shutdown Voltage Dip at Input Undervoltage Secondary Spike Overload at Output
Figure 5. Reset Timing
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Table 1. DPAK 5-Lead Thermal RC Network Models
Drain Copper Area (1 oz thick) (SPICE Deck Format) 168 C_C1 C_C2 C_C3 C_C4 C_C5 C_C6 C_C7 C_C8 C_C9 C_C10 Junction node1 node2 node3 node4 node5 node6 node7 node8 node9 Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd 168 mm2 mm2 736 mm2 mm2 168 mm2 736 mm2 Cauer Network 736 Units W-s/C W-s/C W-s/C W-s/C W-s/C W-s/C W-s/C W-s/C W-s/C W-s/C R's C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W 0.0123 0.0585 0.0304 0.3997 3.115 3.571 12.851 35.471 46.741 R's 0.0123 0.0585 0.0287 0.3772 2.68 1.38 5.92 7.39 28.94 C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W Tau 1.36E-08 7.41E-07 1.04E-05 3.91E-05 1.80E-03 3.77E-01 3.79E+00 2.65E+01 8.71E+01 Foster Network Tau 1.361E-08 7.411E-07 1.029E-05 3.737E-05 1.376E-03 2.851E-02 9.475E-01 1.173E+01 8.59E+01 Units sec sec sec sec sec sec sec sec sec sec
1.00E-06 1.00E-05 6.00E-05 1.00E-04 4.36E-04 6.77E-02 1.51E-01 4.80E-01 3.740 10.322 168 mm2
1.00E-06 1.00E-05 6.00E-05 1.00E-04 3.64E-04 1.92E-02 1.27E-01 1.018 2.955 0.438 736 mm2
R_R1 R_R2 R_R3 R_R4 R_R5 R_R6 R_R7 R_R8 R_R9 R_R10 NOTE:
Junction node1 node2 node3 node4 node5 node6 node7 node8 node9
node1 node2 node3 node4 node5 node6 node7 node8 node9 Gnd
0.015 0.08 0.4 0.2 2.97519 8.2971 25.9805 46.5192 17.7808 0.1
0.015 0.08 0.4 0.2 2.6171 1.6778 7.4246 14.9320 19.2560 0.1758
Bold face items represent the package without the external thermal system.
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Table 2. D2PAK 5-Lead Thermal RC Network Models
Drain Copper Area (1 oz thick) (SPICE Deck Format) 241 C_C1 C_C2 C_C3 C_C4 C_C5 C_C6 C_C7 C_C8 C_C9 C_C10 Junction node1 node2 node3 node4 node5 node6 node7 node8 node9 Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd 241 mm2 mm2 788 mm2 mm2 241 mm2 788 mm2 Cauer Network 653 Units W-s/C W-s/C W-s/C W-s/C W-s/C W-s/C W-s/C W-s/C W-s/C W-s/C R's C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W 0.0123 0.0585 0.0257 0.3413 1.77 1.54 4.13 6.27 60.80 R's 0.0123 0.0585 0.0260 0.3438 1.81 1.52 3.46 5.03 29.30 C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W Tau 1.361E-08 7.411E-07 1.005E-05 3.460E-05 7.868E-04 7.431E-03 2.786E+00 2.014E+01 1.134E+02 Foster Network Tau 1.361E-08 7.411E-07 1.007E-05 3.480E-05 8.107E-04 7.830E-03 2.012E+00 2.601E+01 1.218E+02 Units sec sec sec sec sec sec sec sec sec sec
1.00E-06 1.00E-05 6.00E-05 1.00E-04 2.82E-04 5.58E-03 4.25E-01 9.22E-01 1.73 7.12 241 mm2
1.00E-06 1.00E-05 6.00E-05 1.00E-04 2.87E-04 5.95E-03 4.61E-01 2.05 4.88 1.31 653 mm2
R_R1 R_R2 R_R3 R_R4 R_R5 R_R6 R_R7 R_R8 R_R9 R_R10 NOTE:
Junction node1 node2 node3 node4 node5 node6 node7 node8 node9
node1 node2 node3 node4 node5 node6 node7 node8 node9 gnd
0.015 0.08 0.4 0.2 1.85638 1.23672 9.81541 33.1868 27.0263 1.13944
0.0150 0.0800 0.4000 0.2000 1.8839 1.2272 5.3383 18.9591 13.3369 0.1191
Bold face items represent the package without the external thermal system.
The Cauer networks generally have physical significance and may be divided between nodes to separate thermal behavior due to one portion of the network from another. The Foster networks, though when sorted by time constant (as above) bear a rough correlation with the Cauer networks, are really only convenient mathematical models. Cauer networks can be easily implemented using circuit simulating tools, whereas Foster networks may be more easily implemented using mathematical tools (for instance, in a spreadsheet program), according to the following formula:
R(t) +
S Ri 1-e-t taui i+1
n
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NCV4275
110 100 90 qJA (C/W) qJA (C/W) 80 70 60 50 40 30 150 200 250 300 350 400 450 500 550 600 650 700 750 COPPER AREA (mm2) 2 oz 1 oz 110 100 90 80 70 60 50 40 30 150 200 250 300 350 400 450 500 550 600 650 700 750 COPPER AREA (mm2) 2 oz 1 oz
Figure 6. qJA vs. Copper Spreader Area, DPAK 5-Lead
Figure 7. qJA vs. Copper Spreader Area, D2PAK 5-Lead
100 Cu Area 167 mm2 10 R(t) C/W Cu Area 736 mm2
1.0 sqrt(t) 0.1
0.01 0.0000001
0.000001
0.00001
0.0001
0.001
0.01 TIME (sec)
0.1
1.0
10
100
1000
Figure 8. Single-Pulse Heating Curves, DPAK 5-Lead
100 Cu Area 167 mm2 10 R(t) C/W Cu Area 736 mm2
1.0
0.1
0.01 0.0000001
0.000001
0.00001
0.0001
0.001
0.01 TIME (sec)
0.1
1.0
10
100
1000
Figure 9. Single-Pulse Heating Curves, D2PAK 5-Lead
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100 50% Duty Cycle 20% RqJA 736 mm2 C/W 10 10% 5% 2% 1%
1.0
0.1 Non-normalized Response 0.01 0.0000001 0.000001 0.00001 0.0001 0.001 0.01 0.1 1.0 10 100 1000
PULSE WIDTH (sec)
Figure 10. Duty Cycle for 1" Spreader Boards, DPAK 5-Lead
100 50% Duty Cycle RqJA 788 mm2 C/W 10 20% 10% 5% 1.0 2% 1%
0.1 Non-normalized Response 0.01 0.0000001 0.000001 0.00001 0.0001 0.001 0.01 0.1 1.0 10 100 1000
PULSE WIDTH (sec)
Figure 11. Duty Cycle for 1" Spreader Boards, D2PAK 5-Lead
Junction
R1
R2
R3
Rn
C1
C2
C3
Cn Ambient (thermal ground)
Time constants are not simple RC products. Amplitudes of mathematical solution are not the resistance values.
Figure 12. Grounded Capacitor Thermal Network ("Cauer" Ladder)
Junction
R1
R2
R3
Rn
C1
C2
C3
Cn
Each rung is exactly characterized by its RC-product time constant; amplitudes are the resistances.
Ambient (thermal ground)
Figure 13. Non-Grounded Capacitor Thermal Ladder ("Foster" Ladder)
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PACKAGE DIMENSIONS
DPAK 5 CENTER LEAD CROP DT SUFFIX CASE 175AA-01 ISSUE O
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.020 0.028 0.018 0.023 0.024 0.032 0.180 BSC 0.034 0.040 0.018 0.023 0.102 0.114 0.045 BSC 0.170 0.190 0.185 0.210 0.025 0.040 0.020 --- 0.035 0.050 0.155 0.170 MILLIMETERS MIN MAX 5.97 6.22 6.35 6.73 2.19 2.38 0.51 0.71 0.46 0.58 0.61 0.81 4.56 BSC 0.87 1.01 0.46 0.58 2.60 2.89 1.14 BSC 4.32 4.83 4.70 5.33 0.63 1.01 0.51 --- 0.89 1.27 3.93 4.32
-T- B V R C E
SEATING PLANE
R1
S
A
1234 5
Z U
K F L D G
5 PL
J H 0.13 (0.005)
M
DIM A B C D E F G H J K L R R1 S U V Z
T
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PACKAGE DIMENSIONS
D2PAK 5 LEAD DS SUFFIX CASE 936A-02 ISSUE B
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. TAB CONTOUR OPTIONAL WITHIN DIMENSIONS A AND K. 4. DIMENSIONS U AND V ESTABLISH A MINIMUM MOUNTING SURFACE FOR TERMINAL 6. 5. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH OR GATE PROTRUSIONS. MOLD FLASH AND GATE PROTRUSIONS NOT TO EXCEED 0.025 (0.635) MAXIMUM. DIM A B C D E G H K L M N P R S U V INCHES MIN MAX 0.386 0.403 0.356 0.368 0.170 0.180 0.026 0.036 0.045 0.055 0.067 BSC 0.539 0.579 0.050 REF 0.000 0.010 0.088 0.102 0.018 0.026 0.058 0.078 5 _ REF 0.116 REF 0.200 MIN 0.250 MIN MILLIMETERS MIN MAX 9.804 10.236 9.042 9.347 4.318 4.572 0.660 0.914 1.143 1.397 1.702 BSC 13.691 14.707 1.270 REF 0.000 0.254 2.235 2.591 0.457 0.660 1.473 1.981 5 _ REF 2.946 REF 5.080 MIN 6.350 MIN
-T- A K B
12345 OPTIONAL CHAMFER
TERMINAL 6
E
U V
S H M L
D 0.010 (0.254)
M
T
N G R
P
C
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